1. Field of the Invention
The present invention relates to a solid-state imaging apparatus, and particularly to a solid-state imaging apparatus aiming for low power consumption of an output circuit.
2. Description of Related Art
In recent years, in an electronic equipment using a solid-state imaging apparatus such as a digital camera, a copier, and a scanner, there is a distinct move towards increasing the number of pixels as well as achieving higher speed. Along with the move, amount of current that flows in an output circuit of a solid-state imaging apparatus increases. The increase in the amount of current causes to increase power consumption in a solid-state imaging apparatus and calorific value.
FIG. 4 is a view showing a general linear image sensor. Charges photoelectric converted and accumulated in an array of light receiving devices 200 is read out to a shift register 202 through a readout gate 201 that is supplied with a readout gate pulse φTG. The charge read out to the CCD shift register is sequentially transferred and converted into a signal voltage in a signal charge detection unit 203 formed in a floating diffusion region, that converts a signal charge into a signal voltage. The converted signal voltage is outputted to the outside by an output circuit 204 which is comprised of an analog circuit including a source follower and an inverter etc.
FIG. 5 is a waveform chart showing the readout gate pulse φTG and an output signal Vout. In order to speed up, a transfer rate of the CCD shift register must be increased so as to shorten the time needed to read out the signal charge of the light receiving portion. Further, a cycle of the φTG pulse must be shortened. The time needed to read out data in one line must be shortened in this way.
To shorten the time needed to read out the signal charge in each light receiving device, frequency characteristic of an output circuit comprised of an analog circuit must also be increased. Specifically, for a transistor included in the output circuit, a gate length L must be shortened and a gate width W must be widened to increase a frequency characteristic of a source follower and the like. However it increases an amount of current that flows the output circuit, thereby inducing to increase calorific value.
Further, an amount of the charge Q photoelectric converted at the array light receiving portion can be expressed as;Q=η×L×Ttg wherein L is a quantity of light, η is a photoelectric conversion efficiency, and Ttg is a time for accumulating charge.
By increasing the number of reading out the charge photoelectric converted and accumulated in the light receiving portion to the CCD shift register in order to speed up, the time for the light receiving portion to accumulate charges in the light receiving portion Ttg is shortened. Accordingly, if the quantity of light in light source remains the same, the amount of charge photoelectric converted Q is consequently reduced due to higher speed. If the amount of charge is reduced, necessary amplitude as an output voltage (dynamic range) cannot be obtained, thus a gain of an output circuit must be increased. This indicates that the number of transistors in a circuit needs to be increased, accordingly increasing power consumption. Even if the quantity of light is increased to complement it, there is another problem that power consumption in a light source increases.
As described in the foregoing, a problem of increasing power consumption is unavoidable for speeding up.
One method of resolving the problem of increasing power consumption for an output circuit is disclosed in Japanese Unexamined Patent Application Publication No. 10-117306. An output circuit disclosed in Japanese Unexamined Patent Application Publication No. 10-117306 is shown in FIG. 6. FIG. 6 shows a signal charge detection unit and an output circuit for the solid-state imaging apparatus shown in FIG. 4, and a reset circuit that is not shown in FIG. 4. Signal charges sequentially transferred are converted into signal voltage in a signal charge detection portion 2, and outputted to the outside through the output circuit 103. The reset circuit 1 is to reset a potential of the signal charge detection portion 2 and output each signal charge being sequentially transferred to specify a reset potential. The output circuit 103 for amplifying the signal voltage is comprised of two-stage source follower 4 and 105. The source follower 4 connects a constant current source 7 to a source side of a transistor 6. The source follower 105 connects a constant current source 109 to a source side of a transistor 8. Further, a power supply voltage VOD 1 to be supplied to a first stage source follower 4 is used in common with a power supply voltage VRD to be supplied to a reset circuit 1. Further, by making a power supply voltage VOD 2 to be supplied to the second stage source follower 105 lower than the power supply voltage VOD 1 to be supplied to the first stage source follower 4, the power consumption is reduced.
However as in a case above, if a potential of the power supply voltage VOD 2 of the second stage source follower 105 is made to be different from a potential of the power supply voltage VRD of the reset circuit 1 and a potential of the power supply voltage VOD 1 of the first stage source follower 4, with the voltages being supplied externally, the power supply voltages may fluctuate independently. Generally, if a voltage inputted to a source follower remains the same, a fluctuation of an output voltage from the source follower caused by a fluctuation of power supply voltage is not large enough to be a problem. However a fluctuation of reset potential VRD fluctuates an input potential of the source follower 105, thereby fluctuating an amplitude range (dynamic range) of an output voltage. For example as shown in FIG. 7, if an input potential of a source follower fluctuates to a lower potential, an amplitude range of an output voltage becomes narrow.
Especially as shown in FIG. 8, in a case an inverter circuit 120 is provided as a subsequent circuit of the source follower 105 so as to increase a gain of an output circuit, an influence from a fluctuation of power supply voltage becomes large. The more an amplification gain of the inverter circuit 120 increases, the narrower a range becomes for an input voltage of the inverter circuit is able to input. Accordingly, if the output voltage of the source follower fluctuates due to a fluctuation of the reset potential VRD, the input voltage of the inverter circuit fluctuates, and the input voltage may go outside a range for the inverter circuit is able to input. The output circuit correspondingly may not operate. Even if the input voltage is within a range in which the inverter circuit is able to input, an amplitude range (dynamic range) of an output voltage from a source follower may need to be narrowed in comparison to a case comprising only source followers. These issues impose restrictions on a gain and a dynamic range of an output circuit, thus create a major problem in designing an output circuit having a higher gain and a wider dynamic range.